As miniaturization of electronic parts is in progress and a higher degree of integration has been therefore demanded, packages are transferred from peripheral terminal packaging and area terminal packaging to three-dimensional packaging. Accordingly, with semiconductor chips and interposers, electric conduction or junction with TSV (through silicon via) has been under study for putting into practical use. For the TSV (through silicon via), it is required to fill via holes with a copper plated film by electrolytic copper plating like copper damascene or via filling of printed circuit boards. In printed circuit boards, it becomes necessary to simultaneously carry out via filling and through-hole plating.
The copper sulfate plating bath used in a via fill plating technique makes use, as additives, of an accelerator called brightener and made of a sulfur-containing organic compound, a carrier made of a polyether compound, and a suppresser called leveler and made of a nitrogen-containing compound. Generally, the brightener is fast in diffusion rate and the carrier and leveler are slower in diffusion rate than the former. Conventionally, the copper sulfate plating bath for via fill has made use of a leveler whose diffusion rate is especially slow as selected among levelers, with which there has been adopted a technique wherein plating deposition on a surface side of a via hole substrate (an upper end portion at a side face of the via holes) is suppressed thereby filling the inside of the via holes by plated copper.
Where via holes having a small diameter or deep via holes are filled with plated copper according to such a technique, a difference in potential between the surface side and the bottom of the via hole substrate becomes great thereby worsening a current distribution inside the via holes. Accordingly, if no effects of the additives are expected, deposition in the vicinity of the surface becomes larger than at the bottom to cause voids to occur. Thus, filling with plated copper is not possible. In addition, with respect to the difference in concentration gradient caused by diffusion in the plating bath, i.e. the thickness of the diffusion layer, where the via hole has a small diameter or depth, the difference between the vicinity of the surface and the bottom of the via hole becomes great, resulting in a thick via bottom.
Via fill plating utilizes a difference in diffusion rate between the leveler and the brightener so as to perform fill plating of copper in via holes. The diffusion rate of the leveler is slower than that of the brightener, so that the leveler is supplied to a thin surface of the diffusion layer and a surface side of the via holes thereby permitting a suppressing action to develop. At the bottom side of the via holes at which the diffusion layer is thick, the leveler does not follow the supply of the brightener and thus, the accelerating action becomes predominant, under which a film grows predominantly from the bottom side of the via holes and the via holes are filled with plated copper.
In this technique of making use of the action of the leveler, an optimum value of the difference in diffusion rate between the surface side and the bottom side of the via hole required for the leveler differs depending on the size of the via hole, i.e. a diameter and depth of an opening and an aspect ratio, so that it has been necessary to find out a leveler exhibiting a good fill plating capability after testing a number of levelers for different via holes.
In this manner, in order not to cause plating failures such as of voids and the like upon filling with plated copper, it is necessary to optimize the diffusion rate of leveler. However, there exist via holes of a wide variety of sizes for different substrates, for which there has been demanded an electrolytic copper plating bath that is easily controllable in diffusion rate in conformity with the diameter and aspect ratio of via holes formed in a substrate.
It will be noted that the following is related art document information related to this invention.    Patent Document 1: JP-A 2003-253490    Patent Document 2: JP-A 2004-43957    Patent Document 3: U.S. Pat. No. 6,024,857    Patent Document 4: JP-B 51-18894    Patent Document 5: JP-B 57-27190    Patent Document 6: JP-B 58-21035    Patent Document 7: JP-A 5-230687    Patent Document 8: JP-A 2001-73182    Patent Document 9: JP-A 2005-29818    Non-patent Document 1: Hideki Hagiwara and two others, “Practical Application of a Copper Sulfate Plating Solution for Via Filling of Buildup Substrates,” The Surface Finishing Society of Japan, Abstract of the 101st Annual Meeting of the Surface Science of Japan, 21D-5, pp. 232 to 233    Non-patent Document 2: Takuji Matsunami and three others, “Copper Sulfate Plating Additives for Via Filling,” MES2000 (the Tenth Microelectronics Symposium) Collected Papers, November, 2000, pp. 39 to 42    on-patent Document 3: Norihiro Yamakawa and three others, “Shape Control for Via Conduction Plating,” MES1999 (the 9th Microelectronics Symposium) Collected Papers, October, 1999, pp. 209 to 212    Non-patent Document 4: Ken Kobayashi and four others. “Study on a Bath Composition Influencing Via Filling Capability by Electrolytic Copper Plating,” Journal of Japan Institute of Electronic Packaging, 2000, Vol. 3, No. 4, pp. 324 to 329    on-patent Document 5: “Current Status and Future Prospect of Copper Sulfate Plating,” Text for the 60th Surface Technology Academic Study and Discussion Conference, The Surface Finishing Society of Japan, November, Heisei 13 (2001), p. 2